Turbo-schedule for LDPC decoding

Alexandre De Baynast, Predrag Radosavljevic, Joseph R. Cavallaro, Ashutosh Sabharwal

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

A major drawback of the low density parity-check codes (LDPC) versus the turbo-codes is their comparative low convergence speed: 30 iterations vs. 8-10 iterations for the turbo-codes. Recently, Hocevar showed by simulations that the convergence rate of the LDPC decoder can be accelerated by exploiting a 'turbo-scheduling' for the bit-node messages. In this paper, we extend this principle 1) for the check messages, 2) for both check and bit nodes messages alternatively (hybrid version). We compare the convergence speed of these schedules by performing the Density Evolution Analysis. Results show that that the convergence rate is about two times increased for most of the LDPC codes in comparison with the standard message passing. Simulations validate the effectiveness of the proposed schedules.

Original languageEnglish (US)
Title of host publication43rd Annual Allerton Conference on Communication, Control and Computing 2005
PublisherUniversity of Illinois at Urbana-Champaign, Coordinated Science Laboratory and Department of Computer and Electrical Engineering
Pages1805-1814
Number of pages10
ISBN (Electronic)9781604234916
StatePublished - 2005
Event43rd Annual Allerton Conference on Communication, Control and Computing 2005 - Monticello, United States
Duration: Sep 28 2005Sep 30 2005

Publication series

Name43rd Annual Allerton Conference on Communication, Control and Computing 2005
Volume4

Other

Other43rd Annual Allerton Conference on Communication, Control and Computing 2005
Country/TerritoryUnited States
CityMonticello
Period9/28/059/30/05

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Computer Science Applications

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